1. Field of the Invention
The present invention relates to high voltage operating field effect transistors, bias circuits for the transistors and high voltage circuits having the transistors. The high voltage operating field effect transistor is a transistor which operates at a voltage an absolute value of which is larger than that of a withstand voltage of a transistor designed for a standard power supply voltage in an IC or an LSI.
2. Description of the Related Art
In a conventional high voltage field effect transistor, as shown in FIG. 1, a high withstand voltage drain region 380 or a field plate 580 biased at a high electric potential is provided on a high withstand insulating film 480 to improve a drain withstand voltage. When a gate length of a field effect transistor used as a standard transistor in an MOSIC or an MOSLSI becomes a small size equal to or smaller than submicron, as shown in FIG. 2, a design is made such that the field effect transistor is provided with a lightly doped drain region called a lightly doped drain (LDD) or a drain extension 340 so as to withstand a standard power supply voltage. However, the high withstand voltage drain region requires an impurity concentration lower than that of the lightly doped drain region, a length or depth larger than that of the lightly doped drain region, or both of them or all of them. For this reason, in JP 2002-314044 A, a high withstand voltage region is formed by combining three regions which are different in impurity concentration and junction depth from each other. Note that, in FIGS. 1 and 2, reference numeral 100 designates a semiconductor substrate, reference numeral 200 designates a source region, reference numeral 300 designates a drain region, reference numeral 400 designates a gate insulating film, and reference numeral 500 designates a conductive gate.
In this case, when the high withstand voltage field effect transistors are integrated into an IC or an LSI, additional photo masks and additional manufacturing processes for forming a high withstand voltage insulating film and a high withstand voltage drain region are required, which leads to high cost. In addition, though increased high withstand voltage is possible for a transistor having such a structure, reduction of a driving current becomes a problem. Also, while a channel length of a field effect transistor for a standard voltage having the drain extension structure or the LDD structure can be increased to improve the withstand voltage, a degree of the improvement is low, and the driving current decreases nearly inversely proportional to the channel length. When a gate insulating film of this field effect transistor for a standard voltage is used, the withstand voltage of the field effect transistor is limited by a withstand voltage as well of this insulating film. Moreover, in case of a transistor which is formed in a semiconductor thin film on an insulating substrate such as silicon on insulator (SOI), a high electric field is concentrated in the thin film at a drain end of a channel. Thus, increasing a drain withstand voltage and maintaining a large output current by using the prior art are even more difficult than in the case of the transistor formed in the semiconductor substrate.